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freescale semiconductor data sheet: advance information document number: mc9s08gw64 rev. 1, 5/2010 ? freescale semiconductor, inc., 2010. all rights reserved. preliminary-subject to change without notice this document contains information on a prod uct under development. freescale reserves the right to change or discontinue this product without notice. mc9s08gw64 80-lqfp case 917a 14 14 64-lqfp case 840f 10 10 8-bit hcs08 central processor unit (cpu) ? new version of s08 core with sa me performace as traditional s08 and lower power ? up to 20 mhz cpu at 3.6 v to 2.15 v and up to 10 mhz cpu at 2.15 v to 1.8 v, across temperature range of ?40 c to 85 c ? hc08 instruction set with added bgnd instruction ? support for up to 48 interrupt/reset sources on-chip memory ? flash read/program/erase over fu ll operating voltage and temperature ? random-access memory (ram) ? security circuitry to prevent una uthorized access to ram and flash contents power-saving modes ? two low power stop modes and reduced power wait mode ? low power run and wait modes allow peripherals to run while voltage regulator is in standby ? peripheral clock gating register can disable clocks to unused modules, thereby reducing currents ? very low power external oscillator th at can be used in stop2 or stop3 modes to provide accurate clock source to real time counter ?6 s typical wakeup time from stop3 mode clock source options ? oscillator (xosc1) ? loop-control pierce oscillator; crystal or ceramic resonator of 32.768 khz; clock source for irtc or ics ? oscillator (xosc2) ? loop-control pierce oscillator; crystal or ceramic resonator range of 31.25 khz to 38.4 khz or 1 mhz to 16 mhz; optional clock source for ics ? internal clock source (ics) ? internal clock source module containing a frequency-locked-loop (fll) controlled by internal or external reference (xosc1, xosc2); precision trimming of internal reference allows 0.2% resolution and 2% deviation over temperature and voltage; supporting cpu/bus frequencies from 1 mhz to 20 mhz system protection ? watchdog computer operating properl y (cop) reset with option to run from dedicated 1 khz internal clock source or bus clock ? low-voltage warn ing with interrupt ? low-voltage detection with reset or interrupt ? illegal opcode and illegal a ddress detection with reset ? flash block protection development support ? single-wire background debug interface ? breakpoint capability to allow single breakpoin t setting during in-circuit debugging (p lus 3 more breakpoints in breakpoint unit) ? breakpoint (bkpt) debug module containing three comparators (a, b, and c) with ability to match ad dresses in 64 kb space. each comparator can be used as ha rdware breakpoint. full mode, comparator a compares address a nd comparator b compares data. supports both tag and force breakpoints peripherals ? lcd ? up to 4 40 or 8 36 lcd driver with inte rnal charge pump and option to provide an internally regulated lc d reference that can be trimmed for contrast control ? adc16 ? two analog-to-digital conv erters; 16-bit resolution; one dedicated differential per adc; up to 16-ch; up to 2.5 s conversion time for 12-bit mode; automatic compare function; hardware averaging; calibration registers; te mperature sensor; internal bandgap reference channel; operation in stop3; fully functional from 3.6 v to 1.8 v ? pracmp ?three rail to rail progra mmable reference analog comparator; up to 8 inputs; on-chip programmable reference generator output; selectable interrupt on ri sing, falling, or either edge of comparator output; operation in stop3 ? sci ? four full duplex non-return to zero (nrz); lin master extended break generation; lin slave extended break detection; wakeup on active edge; sci0 designed for amr operation; txd of sci1 and sci2 can be modulated with timers and rxd can recieved through pracmp; ? spi ? three full-duplex or single-wire bidirectional; double-buffered transmit and receive; master or slave mode; msb-first or lsb-first shifting; spi0 designed for amr opeartion ? iic ? up to 100 kbps with maximu m bus loading; multi-master operation; programmable slave addre ss; interrupt driv en byte-by-byte data transfer; supporting broadcast mode and 10-bit addressing; supporting sm bus functiona lity; can wake from stop3 ? ftm ? 2-channel ftms; selectable inpu t capture, output compare, or buffered edge- or center-a ligned pwm on each channel ? irtc ? independent real-time clock, independent power domain, 32 bytes ram, 32.768 khz input clock optional output to ics, hardware calendar, hardware compensation due to crystal or temperature characteristics, tamper detection and indicator ? pcrc ? 16/32 bit programmable cyclic redundancy check for high-speed crc calculation ? mtim ? two 8-bit and one 16-bit timer s; configurable clock inputs and interrupt generation on overflow ? pdb ? programmable delay block; optimized for scheduling adc conversions ? pcnt ? position counter; working in stop3 mode without waking cpu; can be used to ge nerate waveforms like timer input/output ? 57 gpios including one output-only pin ? eight kbi interrupts with selectable polarity ? hysteresis and configurable pu llup device on all input pins; configurable slew rate and drive strength on all output pins. package options ? 80-pin lqfp, 64-pin lqfp freescale semiconductor data sheet: advance information an energy efficient solution by freescale mc9s08gw64 series covers: mc9s08gw64 and mc9s08gw32
mc9s08gw64 series mcu data sheet, rev. 1 preliminary-subject to change without notice freescale semiconductor 2 revision history to provide the most up-to-date information, the revision of our documents on the world wide web will be the most current. your printed copy may be an earlier revision. to verify you have the latest information available, refer to: http://freescale.com/ the following revision history table summarizes changes contained in this document. rev date description of changes 1 5/26/2010 initial public release related documentation find the most current versions of all documents at: http://www.freescale.com reference manual (mc9s08gw64rm) contains extensive product informati on including modes of operation, memory, resets and interrupts, register defin ition, port pins, cpu, and all module information. 1 devices in the mc9s08gw64 series. . . . . . . . . . . . . . . . . . . .3 2 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 3.2 parameter classification . . . . . . . . . . . . . . . . . . . . . . . .10 3.3 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . .10 3.4 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . .11 3.5 esd protection and latch-up immunity . . . . . . . . . . . .12 3.6 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 3.7 supply current characteristics . . . . . . . . . . . . . . . . . . .18 3.8 external oscillator (xoscvlp) characteristics . . . . . .20 3.9 internal clock source (ics) characteristics . . . . . . . . .21 3.10 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 3.10.1 control timing . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.10.2 timer (tpm/ftm) module timing . . . . . . . . . . 25 3.10.3 spi timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.11 analog comparator (pracmp) electricals . . . . . . . . . 29 3.12 adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.13 vref characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.14 lcd specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.15 flash specifications . . . . . . . . . . . . . . . . . . . . . . . . . 35 4 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.1 device numbering system . . . . . . . . . . . . . . . . . . . . . 36 5 package information and mechanical drawings . . . . . . . . . . 36 table of contents
devices in the mc9s08gw64 series mc9s08gw64 series mcu data sheet, rev. 1 preliminary-subject to change without notice freescale semiconductor 3 1 devices in the mc9s08gw64 series table 1 summarizes the feature set availabl e in the mc9s08gw64 series of mcus. table 1. mc9s08gw64 series features by mcu and package feature mc9s08gw64 mc9s08gw32 package 80-pin lqfp 64-pin lqfp 80-pin lqfp 64-pin lqfp flash 65,536 bytes 32,768 bytes ram 4,032 bytes 2,048 bytes adc0 1 single-ended channels 7-ch 7-ch 7-ch 7-ch adc0 differential channels 2 1010 adc1 single-ended channels 7-ch 7-ch 7-ch 7-ch adc1 differential channels 1111 bkpt yes yes ics yes yes iic yes yes irq yes yes irtc yes yes kbi 8-ch 8-ch mtim8 2 2 mtim16 yes yes pcnt yes yes pcrc yes yes pdb yes yes pracmp 3 3 sci 4 4 spi 3 3 ftm 2-ch 2-ch lcd 8 36 4 40 8 24 4 28 8 36 4 40 8 24 4 28 vrefo yes yes yes yes xosc 2 2 i/o pins 3 57 45 57 45
mc9s08gw64 series mcu data sheet, rev. 1 preliminary-subject to change without notice devices in the mc9s08gw64 series freescale semiconductor 4 the block diagram in figure 1 shows the structure of th e mc9s08gw64 series mcus. 1 there are two 16-bit adc modules, so two para llel conversions at two channels can be made simultaneously. 2 each differential channel consists of two pins (dadpx and dadmx). 3 the i/o pins include one output-only pin.
devices in the mc9s08gw64 series mc9s08gw64 series mcu data sheet, rev. 1 preliminary-subject to change without notice freescale semiconductor 5 figure 1. mc9s08gw64 series block diagram por t a independent xtal2 internal clock source v refh /v refl v dda /v ssa v dd v ss1 xosc2 gw64 64 kb 8-bit mtim2 cpu v ss2 8-bit mtim1 vreg 2-channel ftm clko port a, d: mosi2 miso2 sci0 port b: rxd0 txd0 pdb extrig kbi port a, f: mtimclk port a, f: mtimclk bkgd/ms lcd iic port a, b: sda scl port a: v refo v bat pcrc port b, d: kbip[7:0] v dda /v ssa v refh /v refl port a,f,g,h: adc1 dadp/m[1] ad[15:2] v dda/ v ssa v refh /v refl port a,f,g,h: dadp/m[0] ad[15:2] ad[20] ad[20] adc0 trig[0] sel[0] trig[1] sel[1] trig[1:0] sel[1:0] xosc1 clko rtc the rtc is in a separate power domain ref clk irclk clock check & select 16-bit mtim3 port a, f: mtimclk resetb ftmclk port a, c, f: ftmch[0:1] sci1 port b, c: rxd1 txd1 sci2 port a, b: rxd2 txd2 sci3 port c, g: rxd3 txd3 pracmp0 pracmp1 pracmp2 pcnt bkpt int cop lv d sim s08 core v6 flash gw32 32 kb gw64 4 kb ram gw32 2 kb xtal1 tamper1 tamper2 port b por t c por t d port e por t f port g por t h pta0/mosi2/pcntch0/scl/ad2 pta1/miso2/pcntch1/sda/ad3 pta2/sclk2/ftmch0/pcnt0/cmpp0 pta4/mtimclk/rxd2/pcnt2/cmpp2 pta5/ftmclk/txd2/extrig/irq pta6/cmpout0/clkout/bkgd/ms pta3/ss2 /ftmch1/pcnt1/cmpp1 ptb0/kbip0/txd1/extal2 ptb1/kbip1/rxd1/xtal2 ptb2/kbip2/mosi0/miso0/rxd0 ptb4/kbip4/sclk0/scl ptb5/kbip5/ss0 /sda ptb6/kbip6/rxd2/lcd0 ptb3/kbip3/miso0/mosi0/txd0 ptb7/kbip7/txd2/lcd1 ptc0/mosi1/lcd2 ptc1/miso1/lcd3 ptc2/sclk1/lcd4 ptc4/ftmch0/rxd1/lcd6 ptc5/ftmch1/txd1/lcd7 ptc6/pcntch0/rxd3/lcd8 ptc3/ss1 /lcd5 ptc7/pcntch1/txd3/lcd9 ptd0/kbip0/mosi2/lcd10 ptd1/kbip1/miso2/lcd11 ptd2/kbip2/sclk2/lcd12 ptd4/kbip4/lcd14 ptd5/kbip5/clkout/lcd15 ptd6/kbip6/lcd16 ptd3/kbip3/ss2 /lcd13 ptd7/kbip7/lcd17 pte0/lcd18 pte1/lcd19 pte2/lcd20 pte4/lcd22 pte5/lcd23 pte6/lcd24 pte3/lcd21 pte7/lcd25 ptf0/lcd26 ptf1/lcd27 ptf2/lcd28 ptf4/lcd30 ptf5/lcd31 ptf6/mtimclk/ad4/lcd32 ptf3/lcd29 ptf7/ftmclk/ad5/lcd33 ptg0/mosi1/ad6/lcd34 ptg1/miso1/ad7/lcd35 ptg2/sclk1/ad8/lcd36 ptg4/cmpout1/rxd3/ad10/lcd38 ptg5/cmpout2/txd3/ad11/lcd39 ptg6/cmpp3/ad12/pcnt0/lcd40 ptg3/ss1 /ad9/lcd37 ptg7/cmpp4/ad13/pcnt1/lcd41 pth0/cmpp5/ad14/pcnt2/lcd42 pth1/rtcclkout/cmpp6/ad15/lcd43 port b, c, d, e, f, g, h: lcd[0:43] sclk2 ss2 port c, g: mosi1 miso1 sclk1 ss1 port b: mosi0 miso0 sclk0 ss0 spi2 spi1 spi0 port a, c: pcnt0 pcnt1 pcnt2 pcntch0 pcntch1 port a, g, h: port a, g, h: port a, g, h: cmpp0/1/2/3/4/5/6 cmpout0 cmpp0/1/2/3/4/5/6 cmpout1 cmpp0/1/2/3/4/5/6 cmpout2 extal2 extal1
mc9s08gw64 series mcu data sheet, rev. 1 preliminary-subject to change without notice pin assignments freescale semiconductor 6 2 pin assignments this section shows the pin assignments for the mc9s08gw64 series devices. figure 2. mc9s08gw64 series in 80-pin lqfp package pte6/lcd24 pte7/lcd25 ptf0/lcd26 ptf1/lcd27 ptf2/lcd28 ptf3/lcd29 ptf4/lcd30 ptf5/lcd31 ptf6/mtimclk/ad4/lcd32 ptf7/ftmclk/ad5/lcd33 ptg0/mosi1/ad6/lcd34 ptg1/miso1/ad7/lcd35 ptg2/sclk1/ad8/lcd36 ptg3/ ss1 /ad9/lcd37 ptg4/cmpout1/rxd3/ad10/lcd38 ptg5/cmpout2/txd3/ad11/lcd39 ptg6/cmpp3/ad12/pcnt0/lcd40 ptg7/cmpp4/ad13/pcnt1/lcd41 pth0/cmpp5/ad14/pcnt2/lcd42 pth1/rtcclkout/ad15/lcd43 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 v dda v refh v ssa v refl dadp0 dadm0 v refo dadp1 dadm1 v bat extal1 xtal1 ta m p e r 1 ta m p e r 2 pta0/mosi2/pcntch0/scl/ad2 pta1/miso2/pcntch1/sda/ad3 pta2/sclk2/ftmch0/pcnt0/cmpp0 pta3/ss2 /ftmch1/pcnt1/cmpp1 pta4/mtimclk/rxd2/pcnt2/cmpp2 pta5/ftmclk/txd2/extrig/irq ptc7/pcntch1/txd3/lcd9 ptc6/pcntch0/rxd3/lcd8 ptc5/ftmch1/txd1/lcd7 ptc4/ftmch0/rxd1/lcd6 ptc3/ss1 /lcd5 ptc2/sclk1/lcd4 ptc1/miso1/lcd3 ptc0/mosi1/lcd2 ptb7/kbip7/txd2/lcd1 ptb6/kbip6/rxd2/lcd0 ptb5/kbip5/ss0 /sda ptb4/kbip4/sclk0/scl ptb3/kbip3/miso0/mosi0/txd0 ptb2/kbip2/mosi0/miso0/rxd0 reset ptb1/kbip1/rxd1/cmpp6/xtal2 ptb0/kbip0/txd1/extal2 v ss v dd pta6/cmpout0/clkout/bkgd/ms v cap1 v cap2 v ll1 v ll2 v ll3 v ss pte5/lcd23 pte4/lcd22 pte3/lcd21 pte2/lcd20 pte1/lcd19 pte0/lcd18 ptd7/kbip7/lcd17 ptd6/kbip6/lcd16 ptd5/kbip5/clkout/lcd15 ptd4/kbip4/lcd14 ptd3/kbip3/ss2 /lcd13 ptd2/kbip2/sclk2/lcd12 ptd1/kbip1/miso2/lcd11 ptd0/kbip0/mosi2/lcd10 80 lqfp
pin assignments mc9s08gw64 series mcu data sheet, rev. 1 preliminary-subject to change without notice freescale semiconductor 7 figure 3. mc9s08gw64 series in 64-pin lqfp package table 2. pin availability by package pin-count 80 64 port pin default func alt 1 alt 2 alt3 alt4 1 1 pte6 pte6 lcd24 2 2 pte7 pte7 lcd25 3 3 ptf0 ptf0 lcd26 4 4 ptf1 ptf1 lcd27 5ptf2ptf2lcd28 6ptf3ptf3lcd29 pte6/lcd24 pte7/lcd25 ptf0/lcd26 ptf1/lcd27 ptf6/mtimclk/ad4/lcd32 ptf7/ftmclk/ad5/lcd33 ptg0/mosi1/ad6/lcd34 ptg1/miso1/ad7/lcd35 ptg2/sclk1/ad8/lcd36 ptg3/ss1 /ad9/lcd37 ptg4/cmpout1/rxd3/ad10/lcd38 ptg5/cmpout2/txd3/ad11/lcd39 ptg6/cmpp3/ad12/pcnt0/lcd40 ptg7/cmpp4/ad13/pcnt1/lcd41 pth0/cmpp5/ad14/pcnt2/lcd42 pth1/rtcclkout/ad15/lcd43 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 v dda/ v refh v ssa/ v refl v refo dadp1 dadm1 v bat extal1 xtal1 ta m p e r 1 ta m p e r 2 pta0/mosi2/pcntch0/scl/ad2 pta1/miso2/pcntch1/sda/ad3 pta2/sclk2/ftmch0/pcnt0/cmpp0 pta3/ss2 /ftmch1/pcnt1/cmpp1 pta4/mtimclk/rxd2/pcnt2/cmpp2 pta5/ftmclk/txd2/extrig/irq ptc7/pcntch1/txd3/lcd9 ptc6/pcntch0/rxd3/lcd8 ptc5/ftmch1/txd1/lcd7 ptc4/ftmch0/rxd1/lcd6 ptb7/kbip7/txd2/lcd1 ptb6/kbip6/rxd2/lcd0 ptb5/kbip5/ss0 /sda ptb4/kbip4/sclk0/scl ptb3/kbip3/miso0/mosi0/txd0 ptb2/kbip2/mosi0/miso0/rxd0 reset ptb1/kbip1/rxd1/cmpp6/xtal2 ptb0/kbip0/txd1/extal2 v ss v dd pta6/cmpout0/clkout/bkgd/ms v cap1 v cap2 v ll1 v ll2 v ll3 v ss pte5/lcd23 pte4/lcd22 ptd7/kbip7/lcd17 ptd6/kbip6/lcd16 ptd5/kbip5/clkout/lcd15 ptd4/kbip4/lcd14 ptd3/kbip3/ss2 /lcd13 ptd2/kbip2/sclk2/lcd12 ptd1/kbip1/miso2/lcd11 ptd0/kbip0/mosi2/lcd10 64 lqfp
mc9s08gw64 series mcu data sheet, rev. 1 preliminary-subject to change without notice pin assignments freescale semiconductor 8 7ptf4ptf4lcd30 8ptf5ptf5lcd31 9 5 ptf6 ptf6 mtimclk ad4 lcd32 10 6 ptf7 ptf7 ftmclk ad5 lcd33 11 7 ptg0 ptg0 mosi1 ad6 lcd34 12 8 ptg1 ptg1 miso1 ad7 lcd35 13 9 ptg2 ptg2 sclk1 ad8 lcd36 14 10 ptg3 ptg3 ss1 ad9 lcd37 15 11 ptg4 ptg4 cmpout1 rxd3 ad10 lcd38 16 12 ptg5 ptg5 cmpout2 txd3 ad11 lcd39 17 13 ptg6 ptg6 cmpp3 ad12 pcnt0 lcd40 18 14 ptg7 ptg7 cmpp4 ad13 pcnt1 lcd41 19 15 pth0 pth0 cmpp5 ad14 pcnt2 lcd42 20 16 pth1 pth1 rtcclkout ad15 lcd43 21 17 v dda v dda 22 v refh v refh 23 18 v ssa v ssa 24 v refl v refl 25 dadp0 dadp0 26 dadm0 dadm0 27 19 v refo v refo 28 20 dadp1 dadp1 29 21 dadm1 dadm1 30 22 v bat v bat 31 23 extal1 extal1 32 24 xtal1 xtal1 33 25 tamper1 1 tamper1 34 26 tamper2 tamper2 35 27 pta0 pta0 mosi2 pcntch0 scl ad2 36 28 pta1 pta1 miso2 pcntch1 sda ad3 37 29 pta2 pta2 sclk2 ftmch0 pcnt0 cmpp0 38 30 pta3 pta3 ss2 ftmch1 pcnt1 cmpp1 39 31 pta4 pta4 mtimclk rxd2 pcnt2 cmpp2 40 32 pta5 2 pta5 ftmclk txd2 extrig irq 41 33 pta6 3 bkgd/ms cmpout0 clkout bkgd/ms table 2. pin availability by package pin-count (continued) 80 64 port pin default func alt 1 alt 2 alt3 alt4
pin assignments mc9s08gw64 series mcu data sheet, rev. 1 preliminary-subject to change without notice freescale semiconductor 9 42 34 v dd v dd 43 35 v ss v ss 44 36 ptb0 ptb0 kbip0 txd1 extal2 45 37 ptb1 1 ptb1 kbip1 rxd1 cmpp6 xtal2 46 38 reset reset 47 39 ptb2 ptb2 kbip2 mosi0 miso0 rxd0 48 40 ptb3 4 ptb3 kbip3 miso0 mosi0 txd0 49 41 ptb4 3 ptb4 kbip4 sclk0 scl 50 42 ptb5 3 ptb5 kbip5 ss0 sda 51 43 ptb6 ptb6 kbip6 rxd2 lcd0 52 44 ptb7 ptb7 kbip7 txd2 lcd1 53 ptc0 ptc0 mosi1 lcd2 54 ptc1 ptc1 miso1 lcd3 55 ptc2 ptc2 sclk1 lcd4 56 ptc3 ptc3 ss1 lcd5 57 45 ptc4 ptc4 ftmch0 rxd1 lcd6 58 46 ptc5 ptc5 ftmch1 txd1 lcd7 59 47 ptc6 ptc6 pcntch0 rxd3 lcd8 60 48 ptc7 ptc7 pcntch1 txd3 lcd9 61 49 ptd0 ptd0 kbip0 mosi2 lcd10 62 50 ptd1 ptd1 kbip1 miso2 lcd11 63 51 ptd2 ptd2 kbip2 sclk2 lcd12 64 52 ptd3 ptd3 kbip3 ss2 lcd13 65 53 ptd4 ptd4 kbip4 lcd14 66 54 ptd5 ptd5 kbip5 clkout lcd15 67 55 ptd6 ptd6 kbip6 lcd16 68 56 ptd7 ptd7 kbip7 lcd17 69 pte0 pte0 lcd18 70 pte1 pte1 lcd19 71 pte2 pte2 lcd20 72 pte3 pte3 lcd21 73 57 pte4 pte4 lcd22 74 58 pte5 pte5 lcd23 75 59 v ss v ss 76 60 v ll3 v ll3 table 2. pin availability by package pin-count (continued) 80 64 port pin default func alt 1 alt 2 alt3 alt4
mc9s08gw64 series mcu data sheet, rev. 1 preliminary-subject to change without notice electrical characteristics freescale semiconductor 10 3 electrical characteristics 3.1 introduction this section contains electrical and timin g specifications for the mc9s08gw64 sries of microcontrollers av ailable at the time of publication. 3.2 parameter classification the electrical parameters shown in this supplement are guaranteed by various methods. to give the customer a better understanding the following cla ssification is used and the parameters are tagge d accordingly in the tables where appropriate: note the classification is shown in the column labeled ?c? in the parameter tables where appropriate. 3.3 absolute maximum ratings absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. stress beyond the limits specified in table 4 may affect device reliability or cause permanent damage to the device. for functional operating conditions, refer to the remaining tables in this section. this device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advise d that normal precautions be taken to av oid application of any voltages higher than maximum-rated voltages to this 77 61 v ll2 v ll2 78 62 v ll1 v ll1 79 63 v cap2 v cap2 80 64 v cap1 v cap1 1 tamper0 pin is dedicatedly used for battery remo val tamper and not exposed on any soc pins. 2 pta5 is with double drive strength. 3 pta6 is an output-only pin when it is configured as gpio. 4 ptb2, ptb3 and ptb4 are compatible with 5 v devices with a pullup device. table 3. parameter classifications p those parameters are guaranteed during produ ction testing on each individual device. c those parameters are achieved by the design charac terization by measuring a statistically relevant sample size across process variations. t those parameters are achieved by design characteri zation on a small sample size from typical devices under typical conditions unless otherwise noted. all va lues shown in the typical column are within this category. d those parameters are derived mainly from simulations. table 2. pin availability by package pin-count (continued) 80 64 port pin default func alt 1 alt 2 alt3 alt4
electrical characteristics mc9s08gw64 series mcu data sheet, rev. 1 preliminary-subject to change without notice freescale semiconductor 11 high-impedance circuit. reliability of operation is enhanced if unused inputs ar e tied to an appropriate logic voltage level (f or instance, either v ss or v dd ) or the programmable pull-up resistor associated with the pin is enabled. 3.4 thermal characteristics this section provides information about ope rating temperature range, power dissipation, and package thermal resistance. power dissipation on i/o pins is usually small compared to the power dissipation in on-chip logic and voltage regulator circuits, and it is user-determined rather than being c ontrolled by the mcu design. to take p i/o into account in power calculations, determine the difference between actual pin voltage and v ss or v dd and multiply by the pin current fo r each i/o pin. except in cases of unusually high pin current (heavy loads), the difference between pin voltage and v ss or v dd will be very small. table 4. absolute maximum ratings rating symbol value unit supply voltage v dd ?0.3 to +3.8 v maximum current into v dd i dd 120 ma digital input voltage v in ?0.3 to v dd +0.3 v instantaneous maximum current single pin limit (applies to all port pins except pta5 and ptb1) 1, 2, 3 1 input must be current limited to the value s pecified. to determine the value of the required current-limiting resistor, calculate resistance values for positive (v dd ) and negative (v ss ) clamp voltages, then use the larger of the two resistance values. 2 all functional non-supply pins are internally clamped to v ss and v dd . 3 power supply must maintain regulation within operating v dd range during instantaneous and operating maximum current conditions. if positive injection current (v in > v dd ) is greater than i dd , the injection current may flow out of v dd and could result in external power supply going out of regulation. ensure external v dd load will shunt current greater than maximum injection current. this will be the greatest risk when the mcu is not consuming power. examples are: if no system clock is present, or if the clock rate is very low (which would reduce overall power consumption). i d 25 ma instantaneous maximum current single pin limit (applies to pta5 and ptb1) 1,2,3 i d 50 ma storage temperature range t stg ?55 to 150 c table 5. thermal characteristics rating symbol value unit operating temperature range (packaged) t a t l to t h ?40 to 85 c maximum junction temperature t j 95 c thermal resistance single-layer board 80-pin lqfp ja tbd c/w 64-pin lqfp tbd thermal resistance four-layer board 80-pin lqfp ja tbd c/w 64-pin lqfp tbd
mc9s08gw64 series mcu data sheet, rev. 1 preliminary-subject to change without notice electrical characteristics freescale semiconductor 12 the average chip-junction temperature (t j ) in c can be obtained from: t j = t a + (p d ja ) eqn. 1 where: t a = ambient temperature, c ja = package thermal resistance, junction-to-ambient, c/w p d = p int + p i/o p int = i dd v dd , watts ? chip internal power p i/o = power dissipation on input and output pins ? user determined for most applications, p i/o << p int and can be neglected. an approximate relationship between p d and t j (if p i/o is neglected) is: p d = k (t j + 273 c) eqn. 2 solving equation 1 and equation 2 for k gives: k = p d (t a + 273 c) + ja (p d ) 2 eqn. 3 where k is a constant pertaining to the particular pa rt. k can be determined from equation 3 by measuring p d (at equilibrium) for a known t a . using this value of k, the values of p d and t j can be obtained by solving equation 1 and equation 2 iteratively for any value of t a . 3.5 esd protection and latch-up immunity although damage from electrostatic discharge (esd) is much less common on these devices th an on early cmos circuits, normal handling precautions should be taken to avoid exposure to st atic discharge. qualification tests are performed to ensure that these devices can withstand exposure to reasonable levels of static without suffering any permanent damage. all esd testing is in conformity with aec-q100 stress test qu alification for automotive grade integrated circuits. during the device qualification, esd stresses were performed for the human body model (hbm), the machine model (mm) and the charge device model (cdm). a device is defined as a failure if after exposure to esd puls es the device no longer meets the device specification. complete dc parametric and functional testing is pe rformed per the applicable device specificat ion at room temperature followed by hot temperature, unless instructed ot herwise in the device specification. table 6. esd and latch-up test conditions model description symbol value unit human body model series resistance r1 1500 storage capacitance c 100 pf number of pulses per pin ? 3 charge device model series resistance r1 0 storage capacitance c 200 pf number of pulses per pin ? 3 latch-up minimum input voltage limit ?2.5 v maximum input voltage limit 7.5 v
electrical characteristics mc9s08gw64 series mcu data sheet, rev. 1 preliminary-subject to change without notice freescale semiconductor 13 3.6 dc characteristics this section includes informatio n about power supply requiremen ts and i/o pin characteristics. table 7. esd and latch-up protection characteristics no. rating 1 1 parameter is achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. symbol min max unit 1 human body model (hbm) v hbm 1500 ? v 2 machine model (mm) v mm 200 ? v 3 charge device model (cdm) v cdm 500 ? v 4 latch-up current at t a = 85 ci lat 100 ? ma table 8. dc characteristics num c characteristic symbol condition min typ 1 max unit 1 operating voltage 1.8 3.6 v 2 c output high voltage all non-lcd pins low-drive strength v oh v dd >1.8 v i load = ?0.6 ma v dd ? 0.5 ? ? v p all non-lcd pins high-drive strength v dd > 2.7 v i load = ?10 ma v dd ? 0.5 ? ? cv dd > 1.8 v i load = ?3 ma v dd ? 0.5 ? ? 3 c output high voltage all lcd/gpio pins low-drive strength v oh v dd >1.8 v i load = ?0.5 ma v dd ? 0.5 ? ? v p all lcd/gpio pins high-drive strength v dd > 2.7 v i load = ?2.5 ma v dd ? 0.5 ? ? cv dd > 1.8 v i load = ?1 ma v dd ? 0.5 ? ? 4 d output high current max total i oh for all ports i oht ??100ma 5 c output low voltage all non-lcd pins low-drive strength v ol v dd > 1.8 v i load = 0.6 ma ??0.5v p all non-lcd pins high-drive strength v dd > 2.7 v i load = 10 ma ??0.5 cv dd > 1.8 v i load = 3 ma ??0.5 6 c output low voltage all lcd/gpio pins low-drive strength v ol v dd > 1.8 v i load = 0.5 ma ??0.5v p all lcd/gpio pins high-drive strength v dd > 2.7 v i load = 3 ma ??0.5 cv dd > 1.8 v i load = 1 ma ??0.5 7 d output low current max total i ol for all ports i olt ??100ma
mc9s08gw64 series mcu data sheet, rev. 1 preliminary-subject to change without notice electrical characteristics freescale semiconductor 14 8 p input high voltage all digital inputs v ih v dd > 2.7 v 0.70 x v dd ??v cv dd > 1.8 v 0.85 x v dd ?? 9 p input low voltage all digital inputs v il v dd > 2.7 v ? ? 0.35 x v dd cv dd > 1.8 v ? ? 0.30 x v dd 10 c input hysteresis all digital inputs v hys 0.06 x v dd ??mv 11 p input leakage current all input only pins (per pin) |i in |v in = v dd or v ss ?0.025 1 a 12 p hi-z (off-state) leakage current all input/output (per pin) |i oz |v in = v dd or v ss ?0.025 1 a 13 p total leakage current 2 total leakage current for all pins |i int |v in = v dd or v ss ?? 2 a 14 p pullup, pulldown resistors all digital inputs, when enabled r pu, r pd 17.5 ? 52.5 k 15 p pullup, pulldown resistors all digital inputs, when enabled r pu, r pd 17.5 ? 52.5 k 16 d dc injection current 3, 4, 5 single pin limit i ic v in < v ss , v in > v dd ?0.2 ? 0.2 ma total mcu limit, includes sum of all stressed pins ?5 ? 5 ma 17 c input capacitance, all pins c in ?? 8pf 18 c ram retention voltage v ram ?0.61.0v 19 c irtc ram retention voltage v iram ?1.05? v 20 c por re-arm voltage 6 v por 0.9 1.4 2.0 v 21 d por re-arm time t por 10 ? ? s 22 c low-voltage detection threshold high range ? v dd falling v lv d h 2.11 2.16 2.22 v high range ? v dd rising 2.16 2.23 2.27 23 c low-voltage detection threshold low range ? v dd falling v lv d l 1.80 1.85 1.91 v low range ? v dd rising 1.86 1.92 1.99 24 c low-voltage warning threshold v dd falling, lvwv = 1 v lv w h 2.36 2.46 2.56 v v dd rising, lvwv = 1 2.52 2.49 2.71 25 c low-voltage warning v dd falling, lvwv = 0 v lv w l 2.10 2.16 2.23 v v dd rising, lvwv = 0 2.15 2.23 2.26 26 c low-voltage inhibit reset/recover hysteresis v hys ?80?mv 27 p bandgap voltage reference 7 v bg 1.15 1.17 1.18 v 1 typical values are measured at 25 c. characterized, not tested table 8. dc characteristics (continued) num c characteristic symbol condition min typ 1 max unit
electrical characteristics mc9s08gw64 series mcu data sheet, rev. 1 preliminary-subject to change without notice freescale semiconductor 15 figure 4. non lcd pins i/o pullup and pulldown typical resistor values (v dd = 3.0 v) figure 5. typical low-side driver (s ink) characteristics(non lcd pins) ? low drive (ptxdsn = 0) 2 total leakage current is the sum value for all gpio pins. this leakage current is not distributed evenly across all pins but characterization data shows that individual pin leakage current maximums are less than 250na. 3 all functional non-supply pins, except for ptb2 are internally clamped to v ss and v dd . 4 input must be current limited to the value sp ecified. to determine the value of the required current-limiting resistor, calcula te resistance values for positive and negative clamp voltages, then use the larger of the two values. 5 power supply must maintain regulation within operating v dd range during instantaneous and operating maximum current conditions. if the positive injection current (v in > v dd ) is greater than i dd , the injection current may flow out of v dd and could result in external power supply going out of regulation. ensure that external v dd load will shunt current greater than maximum injection current. this will be the great est risk when the mcu is not consuming power. examples are: if no system clock is present, or if clock rate is very low (which would reduce overall power consumption). 6 por will occur below the minimum voltage. 7 factory trimmed at v dd = 3.0 v, temp = 25 c pullup resistor 38 39 40 41 42 43 44 45 1.9 2.2 2.5 2.8 3.1 3.4 v dd (v) resistor (kohm) 85c 25c -40c pulldown resistor 37 37.5 38 38.5 39 39.5 40 40.5 41 41.5 1.9 2.2 2.5 2.8 3.1 3.4 v dd (v) resistor (kohm) 85c 25c -40c tbd vol vs iol (low drive) 0.00 0.20 0.40 0.60 0.80 1.00 1.20 1.40 1.60 0135791113151719 iol(ma) vol(v) 85c 25c -40c typical vol vs vdd (iol = 2ma) 0.14 0.19 0.24 0.29 0.34 0.39 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 vdd(v) vol(v) 85c 25c -40c tbd
mc9s08gw64 series mcu data sheet, rev. 1 preliminary-subject to change without notice electrical characteristics freescale semiconductor 16 figure 6. typical low-side driver (sink) characteristics(non lcd pins) ? high drive (ptxdsn = 1) figure 7. typical high-side (source) characteristics (non lcd pins) ? low drive (ptxdsn = 0) figure 8. typical high-side (source ) characteristics(non lcd pins) ? high drive (ptxdsn = 1) typical vol vs vdd 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 vdd(v) vol(v) 85 o c 25 o c -40 o c i ol = 10ma i ol = 6ma i ol = 3ma vol vs iol (high drive) 0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80 0.90 1.00 0 1 3 5 7 9 11 13 15 17 19 iol(ma) vol(v) 85c 25c -40c tbd voh vs ioh (low drive) 0.00 0.20 0.40 0.60 0.80 1.00 1.20 1.40 1.60 1.80 0 -2 -4 -6 -8 -10 -12 -14 -16 -18 -20 ioh(ma) voh(v) 85c 25c -40c typical vdd - voh vs vdd (ioh = -2ma) 0.14 0.24 0.34 0.44 0.54 0.64 0.74 0.84 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 vdd(v) vdd - voh(v ) 85c 25c -40c tbd voh vs ioh (high drive) 0.00 0.20 0.40 0.60 0.80 1.00 1.20 1.40 0 -2 -4 -6 -8 -10 -12 -14 -16 -18 -20 ioh(ma) voh(v) hot room cold typical vdd - voh vs vdd 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 vdd(v) vdd - voh(v ) 85 o c 25 o c -40 o c i oh = -10ma i oh = -6ma i oh = -3ma tbd
electrical characteristics mc9s08gw64 series mcu data sheet, rev. 1 preliminary-subject to change without notice freescale semiconductor 17 figure 9. typical low-side driver (sink) characteristics(lcd/gpio pins) ? low drive (ptxdsn = 0) figure 10. typical low-side driver (s ink) characteristics(lcd/gpio pins) ? high drive (ptxdsn = 1) figure 11. typical high-side (source) characteristics (lcd/gpio pins) ? low drive (ptxdsn = 0) vol vs iol (low drive) 0.00 0.20 0.40 0.60 0.80 1.00 1.20 1.40 1.60 0135791113151719 iol(ma) vol(v) 85c 25c -40c typical vol vs vdd (iol = 2ma) 0.14 0.19 0.24 0.29 0.34 0.39 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 vdd(v) vol(v) 85c 25c -40c tbd typical vol vs vdd 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 vdd(v) vol(v) 85 o c 25 o c -40 o c i ol = 10ma i ol = 6ma i ol = 3ma vol vs iol (high drive) 0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80 0.90 1.00 0 1 3 5 7 9 11 13 15 17 19 iol(ma) vol(v) 85c 25c -40c tbd voh vs ioh (low drive) 0.00 0.20 0.40 0.60 0.80 1.00 1.20 1.40 1.60 1.80 0 -2 -4 -6 -8 -10 -12 -14 -16 -18 -20 ioh(ma) voh(v) 85c 25c -40c typical vdd - voh vs vdd (ioh = -2ma) 0.14 0.24 0.34 0.44 0.54 0.64 0.74 0.84 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 vdd(v) vdd - voh(v ) 85c 25c -40c tbd
mc9s08gw64 series mcu data sheet, rev. 1 preliminary-subject to change without notice electrical characteristics freescale semiconductor 18 figure 12. typical high-side (source) characteristics(lcd/gpio pins) ? high drive (ptxdsn = 1) 3.7 supply current characteristics this section includes information about power supply current in various operating modes. table 9. supply current characteristics num c parameter symbol bus freq v dd (v) typ 1 max unit temp ( c) 1 c run supply current fei mode, all modules on, running from flash ri dd 20 mhz 3 17.4 tbd ma ?40 to 85 c t 2 mhz 2.6 tbd 2 c run supply current fei mode, all modules off, running from flash ri dd 20 mhz 3 10.5 ? ma ?40 to 85 c t 2 mhz 1.6 ? 3 t run supply current lprs=0, all modules off, running from flash ri dd 16 khz fbilp 3 158 ? a ?40 to 85 c t 16 khz fbelp 148 ? 4 t run supply current lprs=1, all modules off; running from flash ri dd 16 khz fbilp 3 160 ? a ?40 to 85 c t 16 khz fbelp 23 ? 5 t run supply current lprs=1, all modules off; running from ram ri dd 16 khz fbilp 3 137 ? a ?40 to 85 c t 16 khz fbelp 8? 6c wait mode supply current, all modules off wi dd 20 mhz 3 5.4 tbd ma ?40 to 85 c c 2 mhz 1.1 tbd 7 t wait mode supply current lprs = 0, all modules off wi dd 16 khz fbilp 3 131 ? a ?40 to 85 c t 16 khz fbelp 3 123 ? a ?40 to 85 c voh vs ioh (high drive) 0.00 0.20 0.40 0.60 0.80 1.00 1.20 1.40 0 -2 -4 -6 -8 -10 -12 -14 -16 -18 -20 ioh(ma) voh(v) hot room cold typical vdd - voh vs vdd 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 vdd(v) vdd - voh(v ) 85 o c 25 o c -40 o c i oh = -10ma i oh = -6ma i oh = -3ma tbd
electrical characteristics mc9s08gw64 series mcu data sheet, rev. 1 preliminary-subject to change without notice freescale semiconductor 19 8 t wait mode supply current lprs = 1, all modules off wi dd 16 khz fbilp 3 159 ? a ?40 to 85 c t 16 khz fbelp 35.6 ? a ?40 to 85 c 9 c stop2 mode supply current s2i dd n/a 3 300 tbd na ?40 to 25 c tbd ? 50 c tbd tbd 70 c tbd ? 85 c c n/a 2 tbd ? ?40 to 25 c tbd ? 70 c tbd ? 85 c 10 p stop3 mode supply current no clocks active s3i dd n/a 3 474 tbd na ?40 to 25 c tbd ? 50 c tbd tbd 70 c tbd ? 85 c c n/a 2 tbd ? ?40 to 25 c tbd ? 70 c tbd ? 85 c 1 typical values are measured at 25 c. characterized, not tested. table 10. stop mode adders num c parameter condition temperature ( c) units -40257085 1 t lpo tbd tbd tbd tbd na 2 t errefsten range = hgo = 0 tbd tbd tbd tbd na 3 t irefsten 1 tbd tbd tbd tbd a 4tlvd 1 lvdse = 1 tbd tbd tbd tbd a 5tpracmp 1 not using the bandgap (bgbe = 0) tbd tbd tbd tbd a 6 t vrefo not using the bandgap (bgbe = 0) tbd tbd tbd tbd a 7 t irtc not using the bandgap (bgbe = 0) tbd tbd tbd tbd a table 9. supply current characteristics num c parameter symbol bus freq v dd (v) typ 1 max unit temp ( c)
mc9s08gw64 series mcu data sheet, rev. 1 preliminary-subject to change without notice electrical characteristics freescale semiconductor 20 3.8 external oscillator (xoscvlp) characteristics reference figure 13 and figure 14 for crystal or resonator circuits. 8tadc 1 adlpc = adlsmp = 1 not using the bandgap (bgbe = 0) tbd tbd tbd tbd a 9 t lcd vireg enabled for contrast control, 1/8 duty cycle, 8x24 configuration for driving 192 segments, 32hz frame rate, no lcd glass connected. tbd tbd tbd tbd a 10 t pcnt 1 32khz clock, without pwm output tbd tbd tbd tbd a 11 t pcnt 1 32khz clock, with pwm output tbd tbd tbd tbd a 1 not available in stop2 mode. table 11. xoscvlp and ics specifications (temperature range = ?40 to 85 c ambient) num c characteristic symbol min typ 1 max unit 1c oscillator crystal or resonator (erefs = 1, erclken = 1) low range (range = 0) high range (range = 1), high gain (hgo = 1) high range (range = 1), low power (hgo = 0) f lo f hi f hi 32 1 1 ? ? ? 38.4 16 8 khz mhz mhz 2 d load capacitors low range (range=0), low power (hgo=0) other oscillator settings c 1, c 2 see note 2 see note 3 3 d feedback resistor low range, low power (range=0, hgo=0) 2 low range, high gain (range=0, hgo=1) high range (range=1, hgo=x) r f ? ? ? ? 10 1 ? ? ? m 4 d series resistor ? low range, low power (range = 0, hgo = 0) 2 low range, high gain (range = 0, hgo = 1) high range, low power (range = 1, hgo = 0) high range, high gain (range = 1, hgo = 1) 8 mhz 4 mhz 1 mhz r s ? ? ? ? ? ? ? 100 0 0 0 0 ? ? ? 0 10 20 k 5 c crystal start-up time 4 low range, low power low range, high gain high range, low power high range, high gain t cstl t csth ? ? ? ? 600 400 5 15 ? ? ? ? ms table 10. stop mode adders (continued) num c parameter condition temperature ( c) units -40257085
electrical characteristics mc9s08gw64 series mcu data sheet, rev. 1 preliminary-subject to change without notice freescale semiconductor 21 figure 13. typical crystal or resonator circuit: high range and low range/high gain figure 14. typical crystal or resonator circuit: low range/low power 3.9 internal clock source (ics) characteristics 6 d square wave input clock frequency (erefs = 0, erclken = 1) fee mode fbe or fbelp mode f extal 0.03125 0 ? ? 20 20 mhz mhz 1 data in typical column was characterized at 3.0 v, 25 c or is typical recommended value. 2 load capacitors ( c 1, c 2 ), feedback resistor ( r f ) and series resistor ( r s ) are incorporated internally when range=hgo=0. 3 see crystal or resonator manufacturer?s recommendation. 4 proper pc board layout procedures must be followed to achieve specifications. table 12. ics frequency specifications (temperature range = ?40 to 85 c ambient) num c characteristic symbol min typ 1 max unit 1 p average internal reference frequency ? factory trimmed at vdd = 3.6 v and temperature = 25 c f int_ft ? 32.768 ? khz 2 p average internal reference frequency - trimmed f int_t 31.25 ? 39.063 khz 3 t internal reference start-up time t irst ?? 6 s table 11. xoscvlp and ics specifications (temperature range = ?40 to 85 c ambient) num c characteristic symbol min typ 1 max unit xoscvlp extal xtal crystal or resonator r s c 2 r f c 1 xoscvlp extal xtal crystal or resonator
mc9s08gw64 series mcu data sheet, rev. 1 preliminary-subject to change without notice electrical characteristics freescale semiconductor 22 4p dco output frequency range - untrimmed f dco_ut 12.8 16.8 21.33 mhz 5p dco output frequency range - trimmed f dco_t 16 ? 20 mhz 6 c resolution of trimmed dco output frequency at fixed voltage and temperature (using ftrim) f dco_res_t ? 0.1 0.2 %f dco 7 c resolution of trimmed dco output frequency at fixed voltage and temperatur e (not using ftrim) f dco_res_t ? 0.2 0.4 %f dco 8 c total deviation from trimm ed dco output frequency over voltage and temperature f dco_t ? + 0.5 -1.0 2 %f dco 9 c total deviation from trimm ed dco output frequency over fixed voltage and temperature range of 0 c to 70 c f dco_t ? 0.5 1 %f dco 10 c fll acquisition time 2 t acquire ?? 1ms 11 c long term jitter of dco output clock (averaged over 2-ms interval) 3 c jitter ? 0.02 0.2 %f dco 1 data in typical column was characterized at 3.0 v, 25 c or is typical recommended value. 2 this specification applies to any time the fll reference s ource or reference divider is changed, trim value changed or changing from fll disabled (fbelp, fbilp) to fll enabled (fe i, fee, fbe, fbi). if a crysta l/resonator is being used as the reference, this specification assumes it is already running. 3 jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f bus . measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. noise injected into the fll circuitry via v dd and v ss and variation in the crystal oscillator frequency increase the c jitter percentage for a given interval. table 12. ics frequency specifications (temperature range = ?40 to 85 c ambient) (continued) num c characteristic symbol min typ 1 max unit
electrical characteristics mc9s08gw64 series mcu data sheet, rev. 1 preliminary-subject to change without notice freescale semiconductor 23 figure 15. deviation of dco output from trimmed frequency (20 mhz, 3.0 v) 3.10 ac characteristics this section describes timing charact eristics for each peripheral system.
mc9s08gw64 series mcu data sheet, rev. 1 preliminary-subject to change without notice electrical characteristics freescale semiconductor 24 3.10.1 control timing figure 16. reset timing table 13. control timing num c rating symbol min typ 1 1 typical values are based on characterization data at v dd = 3.0 v, 25 c unless otherwise stated. max unit 1 d bus frequency (t cyc = 1/f bus )f bus dc ? 20 mhz 2 d internal low power oscillator period t lpo 700 ? 1300 s 3 d external reset pulse width 2 2 this is the shortest pulse that is guaranteed to be recognized as a reset pin request. t extrst 100 ? ? ns 4 d reset low drive t rstdrv 34 x t cyc ??ns 5 d bkgd/ms setup time after issuing background debug force reset to enter user or bdm modes t mssu 500 ??ns 6 d bkgd/ms hold time after issuing background debug force reset to enter user or bdm modes 3 3 to enter bdm mode following a por, bkgd/ms should be held low during the power-up and for a hold time of t msh after v dd rises above v lv d . t msh 100 ?? s 7 d irq pulse width asynchronous path 2 synchronous path 4 4 this is the minimum pulse width that is guaranteed to pass th rough the pin synchronization circuitry. shorter pulses may or may not be recognized. in stop mode, the synchronizer is bypassed so shorter pulses can be recognized. t ilih, t ihil 100 1.5 x t cyc ? ? ? ? ns 8 d keyboard interrupt pulse width asynchronous path 2 synchronous path 4 t ilih, t ihil 100 1.5 x t cyc ? ? ? ? ns 9 c port rise and fall time ? non-lcd pins low output drive (ptxds = 0) (load = 50 pf) 5, 6 slew rate control disabled (ptxse = 0) slew rate control enabled (ptxse = 1) 5 timing is shown with respect to 20% v dd and 80% v dd levels. temperature range ?40 c to 85 c. 6 except for lcd pins in open drain mode. t rise , t fall ? ? 16 23 ? ? ns port rise and fall time ? non-lcd pins high output drive (ptxds = 1) (load = 50 pf) 5 , 6 slew rate control disabled (ptxse = 0) slew rate control enabled (ptxse = 1) t rise , t fall ? ? 5 9 ? ? ns 10 c voltage regulator recovery time t vrr ? 6 10 us t extrst reset pin
electrical characteristics mc9s08gw64 series mcu data sheet, rev. 1 preliminary-subject to change without notice freescale semiconductor 25 figure 17. irq /kbipx timing 3.10.2 timer (tpm/ftm) module timing synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the optional external source to the timer counter. these synchronizers operate from the current bus rate clock. figure 18. timer external clock table 14. tpm input timing no. c function symbol min max unit 1 d external clock frequency f tclk 0f bus /4 hz 2 d external clock period t tclk 4?t cyc 3 d external clock high time t clkh 1.5 ? t cyc 4 d external clock low time t clkl 1.5 ? t cyc 5 d input capture pulse width t icpw 1.5 ? t cyc t ihil irq /kbipx t ilih irq /kbipx t tclk t clkh t clkl tclk t icpw ftmchn t icpw ftmchn
mc9s08gw64 series mcu data sheet, rev. 1 preliminary-subject to change without notice electrical characteristics freescale semiconductor 26 3.10.3 spi timing table 15 and figure 19 through figure 22 describe the timing requirements for the spi system 1,2 . 1.there is 20 pf load on the spi ports. 2.there are three types of spi ports in mc9s08gw64 series. they are ports for amr, ports shared with lcd pads and normal ports. this timing is for normal ports condition. table 15. spi timing no. c function symbol min max unit ? d operating frequency master slave f op f bus /2048 0 f bus /2 f bus /4 hz d spsck period master slave t spsck 2 4 2048 ? t cyc t cyc d enable lead time master slave t lead 1 / 2 1 ? ? t spsck t cyc d enable lag time master slave t lag 1 / 2 1 ? ? t spsck t cyc d clock (spsck) high or low time master slave t wspsck t cyc ? 30 t cyc ? 30 1024 t cyc ? ns ns d data setup time (inputs) master slave t su 30 30 ? ? ns ns d data hold time (inputs) master slave t hi 0 25 ? ? ns ns d slave access time t a ?1t cyc d slave miso disable time t dis ?1t cyc d data valid (after spsck edge) master slave t v ? ? 60 60 ns ns d data hold time (outputs) master slave t ho 0 0 ? ? ns ns d rise time input output t ri t ro ? ? t cyc ? 25 25 ns ns d fall time input output t fi t fo ? ? t cyc ? 25 25 ns ns 1 2 3 4 5 6 7 8 9 10 11 12
electrical characteristics mc9s08gw64 series mcu data sheet, rev. 1 preliminary-subject to change without notice freescale semiconductor 27 figure 19. spi master timing (cpha = 0) figure 20. spi master timing (cpha =1) spsck (output) spsck (output) miso (input) mosi (output) ss 1 (output) ms bin 2 bit 6 . . . 1 lsb in msb out 2 lsb out bit 6 . . . 1 (cpol = 0) (cpol = 1) notes: 2. lsbf = 0. for lsbf = 1, bit or der is lsb, bit 1, ..., bit 6, msb. 1. ss output mode (dds7 = 1, ssoe = 1). 1 2 3 4 5 6 910 11 12 4 9 spsck (output) spsck (output) miso (input) mosi (output) msb in 2 bit 6 . . . 1 lsb in master msb out 2 master lsb out bit 6 . . . 1 port data (cpol = 0) (cpol = 1) port data ss 1 (output) 1. ss output mode (dds7 = 1, ssoe = 1). 2. lsbf = 0. for lsbf = 1, bit order is lsb, bit 1, ..., bit 6, msb. notes: 2 1 12 11 3 4 4 11 12 5 6 9 10
mc9s08gw64 series mcu data sheet, rev. 1 preliminary-subject to change without notice electrical characteristics freescale semiconductor 28 figure 21. spi slave timing (cpha = 0) figure 22. spi slave timing (cpha = 1) spsck (input) spsck (input) mosi (input) miso (output) ss (input) msb in bit 6 . . . 1 lsb in msb out slave lsb out bit 6 . . . 1 (cpol = 0) (cpol = 1) note: slave see note 1 1. not defined but normally msb of character just received. 1 2 3 4 5 6 7 8 9 10 11 12 4 11 12 10 spsck (input) spsck (input) mosi (input) miso (output) msb in bit 6 . . . 1 lsb in msb out slave lsb out bit 6 . . . 1 see (cpol = 0) (cpol = 1) ss (input) note: slave note 1 1. not defined but normally lsb of character just received. 1 2 3 4 5 6 7 8 9 10 11 12 4 11 12
electrical characteristics mc9s08gw64 series mcu data sheet, rev. 1 preliminary-subject to change without notice freescale semiconductor 29 3.11 analog comparator (pracmp) electricals 3.12 adc characteristics these specs all assume seperate v ddad supply for adc and isolated pad segment for adc supplies and differential inputs.. spec?s should be de-rated for v refh = v bg condition. table 16. pracmp electrical specifications n c characteristic symbol min typical max unit 1 d supply voltage v pwr 1.8 ? 3.6 v 2 c supply current (active) (prg enabled) i ddact1 ??60 a 3 c supply current (active) (prg disabled) i ddact2 ??40 a 4 c supply current (acmp and prg all disabled) i dddis ?? 2 na 5 d analog input voltage vain v ss ? 0.3 ? v dd v 6 c analog input offset voltage vaio ? 5 40 mv 7 c analog comparator hysteresis v h 3.0 ? 20.0 mv 8 p analog input leakage current i alkg ?? 1 na 9 c analog comparator initialization delay tainit ? ? 1.0 s 10 c programmable reference generator inputs v in1 (v dd )1.8 ? v dd v 11 c programmable reference generator inputs v in2 (v dd25 )1.8 ? 2.75 v 12 c programmable reference generator setup delay t prgst tbd tbd tbd ns 13 c programmable reference generator step size vstep ?0.25 1 0.25 lsb 14 c programmable reference generator voltage range vprgout v in /32 ? v in v table 17. 16-bit adc operating conditions num charact eristic conditions symb min typ 1 max unit comment 1 supply voltage absolute v dda 1.8 ? 3.6 v 2 delta to v dd (v dd ?v dda ) 2 v dda ?100 0 100 mv 3 ground voltage delta to v ss (v ss ?v ssa ) 2 v ssa ?100 0 100 mv 4 ref voltage high v refh 1.15 v dda v dda v
mc9s08gw64 series mcu data sheet, rev. 1 preliminary-subject to change without notice electrical characteristics freescale semiconductor 30 5 ref voltage low v refl v ssa v ssa v ssa v 6 input voltage v adin v refl ?v refh v 7 input capacit ance 16-bit modes 8/10/12-bit modes c adin ? 8 4 10 5 pf 8 input resista nce r adin ?2 5k 9 analog source resista nce 16 bit modes f adck > 8mhz 4mhz < f adck < 8mhz f adck < 4mhz r as ? ? ? ? ? ? 0.5 1 2 k external to mcu assumes adlsmp=0 10 13/12 bit modes f adck > 8mhz 4mhz < f adck < 8mhz f adck < 4mhz ? ? ? ? ? ? 1 2 5 11 11/10 bit modes f adck > 8mhz 4mhz < f adck < 8mhz f adck < 4mhz ? ? ? ? ? ? 2 5 10 12 9/8 bit modes f adck > 8mhz f adck < 8mhz ? ? ? ? 5 10 13 adc convers ion clock freq. adlpc = 0, adhsc = 1 f adck 1.0 ? 10 mhz 14 adlpc = 0, adhsc = 0 1.0 ? 5 15 adlpc = 1, adhsc = 0 1.0 ? 2.5 1 typical values assume v dda = 3.0 v, temp = 25 c, f adck = 1.0 mhz unless otherwise stated. typical values are for reference only and are not tested in production. 2 dc potential difference. table 17. 16-bit adc operating conditions num charact eristic conditions symb min typ 1 max unit comment
electrical characteristics mc9s08gw64 series mcu data sheet, rev. 1 preliminary-subject to change without notice freescale semiconductor 31 figure 23. adc input impedance equivalency diagram table 18. 16-bit adc characteristics full operating range(v refh = v ddad , v refl = v ssad , f adck < 10mhz) characteristic conditions 1 1 all accuracy numbers assume th e adc is calibrated with v refh = v ddad csymb min typ 2 2 typical values assume v ddad = 3.0v, temp = 25 c, f adck = 2.0 mhz unless otherwise stated. typical values are for reference only and are not tested in production. max unit comment supply current adlpc = 1, adhsc = 0 ti dda ?215? a adlsmp = 0 adco = 1 adlpc = 0, adhsc = 0 ? 540 ? adlpc=0, adhsc=1 ? 610 ? supply current stop, reset, module off c i dda ? 0.072 ? a adc asynchronous clock source adlpc = 1, adhsc = 0 pf adack ?2.4? mhz t adack = 1/f adack adlpc = 0, adhsc = 0 ? 5.2 ? adlpc = 0, adhsc = 1 ? 6.2 ? sample time see reference manual for sample times conversion time see reference manual for conversion times + ? + ? v as r as c as v adin z as pad leakage due to input protection z adin simplified input pin equivalent circuit r adin adc sar engine simplified channel select circuit input pin r adin c adin input pin r adin input pin r adin
mc9s08gw64 series mcu data sheet, rev. 1 preliminary-subject to change without notice electrical characteristics freescale semiconductor 32 table 19. 16-bit adc characteristics(v refh = v ddad > 2.7v, v refl = v ssad , f adck < 4mhz, adhsc=1) characteristic conditions 1 csymb min typ 2 max unit comment to t a l unadjusted error 16-bit differential mode 16-bit single-ended mode ttue ? ? 16 20 + 24/-24 + 32/-20 lsb 3 32x hardware averaging (avge = %1 avgs = %11) 13-bit differential mode 12-bit single-ended mode t? ? 1.5 1.75 2.0 2.5 11-bit differential mode 10-bit single-ended mode t? ? 0.7 0.8 1.0 1.25 9-bit differential mode 8-bit single-ended mode t? ? 0.5 0.5 1.0 1.0 differential non-linearity 16-bit differential mode 16-bit single-ended mode t dnl ? ? 2.5 2.5 3 3 lsb 2 13-bit differential mode 12-bit single-ended mode t? ? 0.7 0.7 1 1 11-bit differential mode 10-bit single-ended mode t? ? 0.5 0.5 0.75 0.75 9-bit differential mode 8-bit single-ended mode t? ? 0.2 0.2 0.5 0.5 integral non-linearity 16-bit differential mode 16-bit single-ended mode tinl ? ? 6.0 10.0 12.0 16.0 lsb 2 13-bit differential mode 12-bit single-ended mode t? ? 1.0 1.0 2.0 2.0 11-bit differential mode 10-bit single-ended mode t? ? 0.5 0.5 1.0 1.0 9-bit differential mode 8-bit single-ended mode t? ? 0.3 0.3 0.5 0.5 zero-scale error 16-bit differential mode 16-bit single-ended mode te zs ? ? 4.0 4.0 +16/0 +16/-38 lsb 2 v adin = v ssad 13-bit differential mode 12-bit single-ended mode t? ? 0.7 0.7 2.0 2.0 11-bit differential mode 10-bit single-ended mode t? ? 0.4 0.4 1.0 1.0 9-bit differential mode 8-bit single-ended mode t? ? 0.2 0.2 0.5 0.5
electrical characteristics mc9s08gw64 series mcu data sheet, rev. 1 preliminary-subject to change without notice freescale semiconductor 33 full-scale error 16-bit differential mode 16-bit single-ended mode te fs ? ? +8/0 +12/0 +24/0 +24/0 lsb 2 v adin = v ddad 13-bit differential mode 12-bit single-ended mode t? ? 0.7 0.7 2.0 2.5 11-bit differential mode 10-bit single-ended mode t? ? 0.4 0.4 1.0 1.0 9-bit differential mode 8-bit single-ended mode t? ? 0.2 0.2 0.5 0.5 quantization error 16 bit modes d e q ? -1 to 0 ? lsb 2 < 13 bit modes ? ? 0.5 effective number of bits 16 bit differential mode avg = 32 avg = 16 avg = 8 avg = 4 avg = 1 cenob ? ? ? ? ? 13.5 13.4 13.2 13 12.6 ? ? ? ? ? bits for adc_div=1, adc_clk=10 mhz. 16 bit single-ended mode avg = 32 avg = 16 avg = 8 avg = 4 avg = 1 ? ? ? ? ? 12.39 12.34 12.13 11.94 11.4 ? ? ? ? ? signal to noise plus distortion see enob sinad db total harmonic distortion 16 - bit differential mode avg = 32 cthd ??? db 16 - bit single-ended mode avg = 32 d ??? spurious free dynamic range 16 - bit differential mode avg = 32 csfdr 91.0 96.5 ? db 16 - bit single-ended mode avg = 32 d ??? input leakage error all modes d e il i in * r as mv i in = leakage current (refer to dc characteristics) temp sensor slope ?40 c?25 c d m ? 1.646 ? mv/ c 25 c?125 c ? 1.769 ? temp sensor voltage 25 cdv temp25 ?966?mv table 19. 16-bit adc characteristics(v refh = v ddad > 2.7v, v refl = v ssad , f adck < 4mhz, adhsc=1) characteristic conditions 1 csymb min typ 2 max unit comment sinad 6.02 enob ? 1.76 + =
mc9s08gw64 series mcu data sheet, rev. 1 preliminary-subject to change without notice electrical characteristics freescale semiconductor 34 3.13 vref characteristics 1 all accuracy numbers assume th e adc is calibrated with v refh =v ddad 2 typical values assume v ddad = 3.0 v, temp = 25 c, f adck =2.0mhz unless otherwise stated. typical values are for reference only and are not tested in production. 3 1 lsb = (v refh ?v refl )/2 n table 20. electrical specifications num c characteristic symbol min max unit 1 p supply voltage v dd 1.80 3.60 v 2 p operating temperature range t op ?40 85 c 3 c maximum load 10 ma operation across temperature 4 p voltage output room temp erature untrimmed 1.070?1.202 v 5 p voltage output room temperature factory trimmed 1 1 factory trim is performed at the room temperature. 1.1995?1.2005 v 6 p ?40 c factory trimmed 1.194?1.198 v 7 p 0 c factory trimmed 1.198?1.201 v 8 p 50 c factory trimmed 1.198?1.201 v 9 p 85 c factory trimmed 1.196?1.200 v load bandwidth 10 c load regulation mode = 10 at 1ma load mode = 10 20 100 v/ma 11 c line regulation (power supply rejection) dc 0.1 from room temp voltage mv ac ?60 db power consumption 12 c powered down current (stop mode, vrefen = 0, vrsten = 0) i 100 a 13 c bandgap only (mode[1:0] 00) i 75 a 14 c low power buffer (mode[1:0] 01) i 125 a 15 c tight regulation buffer (mode[1:0] 10) i 1.1 ma 16 c low power and tight regulation (mode[1:0] 11) i1.15ma
electrical characteristics mc9s08gw64 series mcu data sheet, rev. 1 preliminary-subject to change without notice freescale semiconductor 35 3.14 lcd specifications 3.15 flash specifications this section provides details about program/erase ti mes and program-erase endura nce for the flash memory. program and erase operations do not require any special power sources ot her than the normal v dd supply. for more detailed information about program/erase op erations, see the memory section. table 21. lcd electricals, 3-v glass c characteristic symbol min typ max unit d lcd frame frequency f frame 28 30 58 hz d lcd charge pump capacitance c lcd 100 100 nf d lcd bypass capacitance c bylcd 100 100 nf d lcd glass capacitance c glass 2000 8000 pf dv ireg hrefsel = 0 v ireg .89 1.00 1.15 v hrefsel = 1 1.49 1.67 1.85 1 1 v ireg max can not exceed v dd -0.15 v dv ireg trim resolution rtrim 1.5 % v ireg dv ireg ripple hrefsel = 0 .1 v hrefsel = 1 .15 table 22. flash characteristics c characteristic symbol min typical max unit d supply voltage for program/erase -40 c to 85 cv prog/erase 1.8 3.6 v d supply voltage for read operation v read 1.8 3.6 v d internal fclk frequency 1 1 the frequency of this clock is controlled by a software setting. f fclk 150 200 khz d internal fclk period (1/fclk) t fcyc 56.67 s p byte program time (random location) 2 t prog 9t fcyc p byte program time (burst mode) 2 t burst 4t fcyc p page erase time 2 t page 4000 t fcyc p mass erase time 2 t mass 20,000 t fcyc d byte program current 3 r iddbp ?4?ma d page erase current 3 r iddpe ?6?ma c program/erase endurance 4 t l to t h = ?40 c to + 85 c t = 25 c 10,000 ? 100,000 ? ? cycles c data retention 5 t d_ret 15 100 ? years
mc9s08gw64 series mcu data sheet, rev. 1 preliminary-subject to change without notice ordering information freescale semiconductor 36 4 ordering information this section contains the ordering information and the device numbering system for the mc9s08gw64 series. 4.1 device numbering system example of the device numbering system: 5 package information and mechanical drawings table 23 provides the available package types and their document numbers. the latest package outline/mechani cal drawings are available on the mc9s08gw64 series product summary pages at http://www.freescale.com . to view the latest drawing, either: ? click on the appropriate link in table 23, or ? open a browser to the freescale ? website ( http://www.freescale.com ), and enter the approp riate document number (from table 23 ) in the ?enter keyword? search box at the top of the page. 2 these values are hardware state machine controlled. user c ode does not need to count cycles. this information supplied for calculating approximate time to program and erase. 3 the program and erase currents are additional to the standard run i dd . these values are measured at room temperatures with v dd = 3.0 v, bus frequency = 4.0 mhz. 4 typical endurance for flash was evaluated for this product family on the 9s12dx64. for additional information on how freescale defines typical endurance, please refer to engineering bulletin eb619, typical endurance for nonvolatile memory . 5 typical data retention values are based on intrinsic capability of the tec hnology measured at high temperature and de-rated to 25 c using the arrhenius equation. for additional information on how freescale defines typical data retention, please refer to engineering bulletin eb618, typical data retention for nonvolatile memory. table 23. package descriptions pin count package type abbreviation designator case no. document no. 80 low quad flat package lqfp lk 917a 98ass23237w 64 low quad flat package lqfp lh 840f 98ass23234w mc temperature range family memory status core (c = ?40 c to 85 c) (9 = flash-based) 9 s08 xx (mc = fully qualified) package designator (see ta b l e 2 3 ) approximate flash size in kb gw 64 c
package information and mechanical drawings mc9s08gw64 series mcu data sheet, rev. 1 preliminary-subject to change without notice freescale semiconductor 37
document number: mc9s08gw64 rev. 1 5/2010 how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor, inc. technical information center, el516 2100 east elliot road tempe, arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor china ltd. exchange building 23f no. 118 jianguo road chaoyang district beijing 100022 china +86 10 5879 8000 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center 1-800-441-2447 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconduc tor@hibbertgroup.com information in this document is provid ed solely to enable system and software implementers to use freescale semiconduc tor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specif ically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data s heets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applic ations intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. rohs-compliant and/or pb-free versions of freescale products have the functionality and electrical characteristics as thei r non-rohs-compliant and/or non-pb-free counterparts. for further information, see http://www.freescale.com or contact your freescale sales representative. for information on freescale?s environmental products program, go to http://www.freescale.com/epp . freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. arm is the registered trademark of arm limited. arm7tdmi-s is the trademark of arm limited. the power architecture and power.org word marks and the power and power.org logos and related marks are trademarks and service marks licensed by power.org ? freescale semiconductor, inc. 2010. all rights reserved. preliminary-subject to change without notice

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